View CYD02S36V_2142277.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary flex36 tm 3.3v 32k/64k/128k/256k/512 x 36 synchronous dual-port ram cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-06076 rev. *b revised january 27, 2005 features ? true dual-ported memory cells that allow simultaneous access of the same memory location ? synchronous pipelined operation ? family of 1-mbit, 2-mbit, 4-mbit, 9-mbit and 18-mbit devices ? pipelined output mode allows fast operation ? 0.18-micron cmos for optimum speed and power ? high-speed clock to data access ? 3.3v low power ? active as low as 225 ma (typ.) ? standby as low as 55 ma (typ.) ? mailbox function for message passing ? global master reset ? separate byte enables on both ports ? commercial and industrial temperature ranges ? ieee 1149.1-compatible jtag boundary scan ? 256-ball fbga (1-mm pitch) ? counter wrap around control ? internal mask register controls counter wrap-around ? counter-interrupt flags to indicate wrap-around ? memory block retransmit operation ? counter readback on address lines ? mask register readback on address lines ? dual chip enables on both ports for easy depth expansion ? seamless migration to next-generation dual-port family functional description the flex36 family includes 1-mbit, 2-mbit, 4-mbit, 9-mbit and 18-mbit pipelined, synchronous, true dual-port static rams that are high-speed, low-power 3.3v cmos. two ports are provided, permitting independent, simultaneous access to any location in memory. a particular port can write to a certain location while another port is reading that location. the result of writing to the same location by more than one port at the same time is undefined. registers on control, address, and data lines allow for minimal set-up and hold time. during a read operation, data is registered for decreased cycle time. each port contains a burst counter on the input address register. after externally loading the counter with the initial address, the counter will increment the address inter- nally (more details to follow). the internal write pulse width is independent of the duration of the r/w input signal. the internal write pulse is self-timed to allow the shortest possible cycle times. a high on ce0 or low on ce1 for on e clock cycle will power down the internal circuitry to reduce the static power consumption. one cycle with chip enables asserted is required to reactivate the outputs. additional features include: r eadback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (cntint ) flags, readback of mask register value on address lines, retransmit functionality, inte rrupt flags for message passing, jtag for boundary scan, and asynchronous master reset (mrst ). the cyd18s36v devices in this family has limited features. please see address counter and mask register opera- tions [18] on page 5 for details. seamless migration to next-generation dual-port family cypress offers a migration path for all devices in this family to the next-generation devices in the dual-port family with a compatible footprint. please contact cypress sales for more details. table 1. product selection guide density 1 mbit (32k x 36) 2 mbit (64k x 36) 4 mbit (128k x 36) 9 mbit (256k x 36) 18 mbit (512k x 36) part number cyd01s36v CYD02S36V cyd04s36v cyd09s36v cyd18s36v max. speed (mhz) 167 167 167 167 133 max. access time ? clock to data (ns) 4.0 4.0 4.0 4.0 5.0 typical operating current (ma) 225 225 225 270 315 package 256 fbga (17 mm x 17 mm) 256 fbga (17 mm x 17 mm) 256 fbga (17 mm x 17 mm) 256 fbga (17 mm x 17 mm) 256 fbga (23 mm x 23 mm)
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 2 of 28 note: 1. 18-mbit device has 19 address bits, 9-mbit device has 18 addre ss bits, 4-mbit device has 17 addr ess bits, 2-mbit device has 1 6 address bits, and 1-mbit device has 15 address bits. logic block diagram [1] ftsel l portstd[1:0] l dq [35:0] l be [3:0] l ce 0 l ce1 l oe l r/w l ftsel r portstd[1:0] r dq [35:0] r be [3:0] r ce 0 r ce1 r oe r r/w r a [18:0] l cnt/msk l ads l cnten l cntrst l ret l cntint l c l wrp l a [18:0] r cnt/msk r ads r cnten r cntrst r ret r cntint r c r wrp r config block config block io control io control dual ported array address & counter logic address & counter logic int l trst tms tdi tdo tck jtag mrst ready r lowspd r ready l lowspd l reset logic int r busy l busy r mailboxes arbitration logic
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 3 of 28 pin configurations 256-ball fbga (top view) cyd01s36v/CYD02S36V/cyd04s36v/cyd09s36v/cyd18s36v 12345678910111213141516 a dq32l dq30l dq28l dq26l dq24l dq22l dq20l dq18l dq 18r dq20r dq22r dq24r dq26r dq28r dq30r dq32r b dq33l dq31l dq29l dq27l dq25l dq23l dq21l dq19l dq 19r dq21r dq23r dq25r dq27r dq29r dq31r dq33r c dq34l dq35l ret l [2,3] int l n c [2,5] n c [2,5] revl [2,4] trst [2,5] mrst vss n c [2,5] n c [2,5] int rret r [2,3] dq35r dq34r d a0l a1l wrp l [2,3] vrefl [2,4] ftsel l [2,3] lowspd l [2,4] vss vttl vttl vss lowspd r [2,4] ftsel r [2,3] vrefl [2,4] wrp r [2,3] a1r a0r e a2l a3l ce0 l [11] ce1l [10] vddiol vddiol vddiol vcore vcore vddior vddior vddior ce1r [10] ce0 r [11] a3r a2r f a4l a5l cntint l [12] be3 l vddiol vss vss vss vss vss vss vddior be3 r cntint r [12] a5r a4r g a6l a7l busy l [2,5] be2 l vddiol vss vss vss vss vss vss vddior be2 r busy r [2,5] a7r a6r h a8l a9l cl vttl vcore vss vss vss vss vss vss vcore vttl cr a9r a8r j a10l a11l vss portstd1 l[2,4] vcore vss vss vss vss vss vss vcore portstd1 r[2,4] vss a11r a10r k a12l a13l oe lbe1 l vddiol vss vss vss vss vss vss vddior be1 roe r a13r a12r l a14l a15l [6] ads l [11] be0 l vddiol vss vss vss vss vss vss vddior be0 r ads r [11] a15r [6] a14r m a16l [7] a17l [8] r/w l revl [2,4] vddiol vddiol vddiol vcore vco re vddior vddior vddior revr [2,4] r/w r a17r [8] a16r [7] n a18l [9] a19l [2,5] cnt/msk l [10] vrefl [2,4] portstd0l [2,4] ready l [2,5] revl [2,3] vttl vttl revr [2,3] ready r [2,5] portstd0r [2,4] vrefr [2,4] cnt/msk r [10] a19r [2,5] a18r [9] p dq16l dq17l cnten l [11] cntrst l [10] n c [2,5] n c [2,5] tck tms tdo tdi n c [2,5] n c [2,5] cntrst r [10] cnten r [11] dq17r dq16r r dq15l dq13l dq11l dq9l dq7l dq5l dq3l dq1l dq 1r dq3r dq5r dq7r dq9r dq11r dq13r dq15r t dq14l dq12l dq10l dq8l dq6l dq4l dq2l dq0l dq 0r dq2r dq4r dq6r dq8r dq10r dq12r dq14r notes: 2. this ball will represent a next generation dual-port feature. fo r more information about this feature, contact cypress sales. 3. connect this ball to vddio. for more information about th is next generation dual-port feature contact cypress sales. 4. connect this ball to vss. for more information about this next generation dual-port feature, contact cypress sales. 5. leave this ball unconnected. for more information about this feature, contact cypress sales. 6. leave this ball unconnected for 32k x 36configuration. 7. leave this ball unconnected for a 64k x 36, 32k x 36 configurations. 8. leave this ball unconnected for a 128k x 36, 64k x 36 and 32k x 36 configurations. 9. leave this ball unconnected for a 256k x 36, 128k x 36, 64k x 36, and 32k x 36 configurations. 10. these balls are not applicable for cyd18s36v device. they need to be tied to vddio. 11. these balls are not applicable for cyd18s36v device. they need to be tied to vss. 12. these balls are not applicable for cyd1 8s36v device. they need to be no connected.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 4 of 28 pin definitions left port right port description a 0l ?a 18l a 0r ?a 18r address inputs . be 0l ?be 3l be 0r ?be 3r byte enable inputs . asserting these signals enabl es read and write operations to the corresponding bytes of the memory array. busy l [2,5] busy r [2,5] port busy output . when the collision is detected, a busy is asserted. c l c r input clock signal . ce0 l [11] ce0 r [11] active low chip enable input . ce1 l [10] ce1 r [10] active high chip enable input . dq 0l ?dq 35l dq 0r ?dq 35r data bus input/output . oe l oe r output enable input . this asynchronous signal must be asserted low to enable the dq data pins during read operations. int l int r mailbox interrup t flag output . the mailbox permits communications between ports. the upper two memory locations can be used for message passing. int l is asserted low when the right port writes to the mailbox location of the left port, and vice versa. an interrupt to a port is de asserted high when it reads the contents of its mailbox. lowspd l [2,4] lowspd r [2,4] port low speed select input . portstd[1:0] l [2,4] portstd[1:0] r [2,4] port address/control/data i/o standard select inputs . r/w l r/w r read/write enable input . assert this pin low to writ e to, or high to read from the dual port memory array. ready l [2,5] ready r [2,5] port ready output . this signal will be asserted when a port is ready for normal operation. cnt/msk l [10] cnt/msk r [10] port counter/mask select input . counter control input. ads l [11] ads r [11] port counter address load strobe input . counter control input. cnten l [11] cnten r [11] port counter enable input . counter control input. cntrst l [10] cntrst r [10] port counter reset input . counter control input. cntint l [12] cntint r [12] port counter interrupt output . this pin is asserted low when the unmasked portion of the counter is incremented to all ?1s?. wrp l [2,3] wrp r [2,3] port counter wrap input . the burst counter wrap control input. ret l [2,3] ret r [2,3] port counter retransmit input . counter control input. ftsel l [2,3] ftsel r [2,3] flow-through select . use this pin to select flow-through mode. when is de-asserted, the device is in pipelined mode. vref l [2,4] vref r [2,4] port external high-sp eed io reference input . v ddiol v ddior port io power supply . rev l [2, 3, 4] rev r [2, 3, 4] reserved pins for future features. mrst master reset input . mrst is an asynchronous input signal and affects both ports. a maser reset operation is required at power-up. trst [2,5] jtag reset input . tms jtag test mode select input . it controls the advance of jtag tap state machine. state machine transitions occur on the rising edge of tck. tdi jtag test data input . data on the tdi input will be shifted serially into selected registers.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 5 of 28 master reset the flex36 family devices undergo a complete reset by taking its mrst input low. the mrst input can switch asynchronously to the clocks. an mrst initializes the internal burst counters to zero, and the counter mask registers to all ones (completely unmasked). mrst also forces the mailbox interrupt (int ) flags and the counter interrupt (cntint ) flags high. mrst must be performed on the flex36 family devices after power-up. mailbox interrupts the upper two memory locations may be used for message passing and permit communications between ports. ta ble 2 shows the interrupt operation for both ports of cyd18s36v. the highest memory location, 7ffff is the mailbox for the right port and 7fffe is the mailbox for the left port. ta ble 2 shows that in order to set the int r flag, a write operation by the left port to address 7ffff will assert int r low. at least one byte has to be active for a write to generate an interrupt. a valid read of the 7ffff location by the right port will reset int r high. at least one byte has to be active in order for a read to reset the interrupt. when one port writes to the other port?s mailbox, the int of the port that the mailbox belongs to is asserted low. the int is reset when the ow ner (port) of the mailbox reads the contents of the mailbox. the interrupt flag is set in a flow-thru mode (i.e., it follows the clock edge of the writing port). also, the flag is reset in a flow-thru mode (i.e., it follows the clock edge of the reading port). each port can read the other port?s mailbox without resetting the interrupt. and each port can write to its own mailbox without setting the interrupt. if an application does not require message passing, int pins should be left open. address counter and mask register operations [18] this section describes the features only apply to 1mbit, 2 mbit, 4 mbit and 9 mbit devices. it do es not apply to 18mbit device. each port of these devices has a programmable burst address counter. the burst counter contains three registers: a counter register, a mask register, and a mirror register. the counter register contains the address used to access the ram array. it is changed only by the counter load, increment, counter reset, and by master reset (mrst ) operations. the mask register value affects the increment and counter reset operations by preventing the corresponding bits of the counter register from changing. it also affects the counter interrupt output (cntint ). the mask register is changed only by the mask load and mask reset operations, and by the mrst . the mask register defines the counting range of the counter register. it divides the counter register into two regions: zero or more ?0s? in the most significant bits define the masked region, one or more ?1s? in the least significant bits define the unmasked region. bit 0 may also be ?0,? masking the least significant counter bit and causing the counter to increment by two instead of one. the mirror register is used to reload the counter register on increment operations (see ?retransmit,? below). it always contains the value last loaded in to the counter register, and is changed only by the counter load, and counter reset opera- tions, and by the mrst . notes: 13. ce is internal signal. ce = low if ce 0 = low and ce 1 = high. for a single read operation, ce only needs to be asserted once at the rising edge of the clk and can be deasserted after that. data will be out after the following clk edge and will be three-stated after the next clk edg e. 14. oe is ?don?t care? for mailbox operation. 15. at least one of be0 , be1 , be2 , or be3 must be low. 16. a17x is a nc for cyd04s36v, therefore the interrupt addresses are 1ffff and 1fffe. a17x and a16x are nc for CYD02S36V, there fore the interrupt addresses are ffff and fffe; a17x, a16x and a15x are nc for cyd01s36v, therefore the interrupt addresses are 7fff and 7ffe. 17. ?x? = ?don?t care,? ?h? = high, ?l? = low. tck jtag test clock input . tdo jtag test data output . tdo transitions occur on the falling edge of tck. tdo is normally three-stated except when captur ed data is shifted out of the jtag tap. v ss ground inputs . v core core power supply . v ttl lvttl power supply for jtag ios pin definitions (continued) left port right port description table 2. interrupt operation example [1, 13, 14, 15, 16, 17] function left port right port r/w l ce l a 0 l ?18 l int l r/w r ce r a 0r?18r int r set right int r flag l l 7ffff x x x x l reset right int r flagxxxxhl7ffffh set left int l flag x x x l l l 7fffe x reset left int l flag h l 7fffe h x x x x
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 6 of 28 table 3 summarizes the operation of these registers and the required input control signals. the mrst control signal is asynchronous. all the other control signals in ta ble 3 (cnt/msk , cntrst , ads , cnten ) are synchronized to the port?s clk. all these counter and mask operations are independent of the port?s chip enable inputs (ce0 and ce1). counter enable (cnten ) inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast, interleaved memory applications. a port?s burst counter is loaded when the port?s address strobe (ads ) and cnten signals are low. when the port?s cnten is asserted and the ads is deasserted, the address counter will increm ent on each low to high transition of that port?s clock signal. this will read/write one word from/into each successive address location until cnten is deasserted. the counter can address the entire memory array, and will loop back to the start. counter reset (cntrst ) is used to reset the unmasked portion of the burst counter to 0s. a counter-mask register is used to control the counter wrap. counter reset operation all unmasked bits of the counter and mirror registers are reset to ?0.? all masked bits remain unchanged. a mask reset followed by a counter reset will reset the counter and mirror registers to 00000, as will master reset (mrst ). counter load operation the address counter and mirror registers are both loaded with the address value presented at the address lines. table 3. address counter and counter-mask register control operation (any port) [17, 19] clk mrst cnt/msk cntrst ads cnten operation description x l x x x x master reset reset address counter to all 0s and mask register to all 1s. h h l x x counter reset reset counter unmasked portion to all 0s. h h h l l counter load load counter with external address value presented on address lines. h h h l h counter readback read out c ounter internal value on address lines. h h h h l counter increment internally increment address counter value. h h h h h counter hold constantly hold the address value for multiple clock cycles. h l l x x mask reset reset mask register to all 1s. h l h l l mask load load mask register with value presented on the address lines. h l h l h mask readback read out mask register value on address lines. h l h h x reserved operation undefined notes: 18. this section describes the cyd09s36v, cyd04s36v, CYD02S36V, and cyd01s36v which have 18, 17, 16 and 15 address bits. 19. counter operation and mask register operation is independent of chip enables.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 7 of 28 counter increment operation once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. only the unmasked bits of t he counter register are incre- mented. the corresponding bit in the mask register must be a ?1? for a counter bit to change. the counter register is incre- mented by 1 if the least significant bit is unmasked, and by 2 if it is masked. if all unmasked bits are ?1,? the next increment will wrap the counter back to the initially loaded value. if an increment results in all the unmasked bits of the counter being ?1s,? a counter interrupt flag (cntint ) is asserted. the next increment will return the counter register to its initial value, which was stored in the mirro r register. the counter address can instead be forced to loop to 00000 by externally connecting cntint to cntrst . [20] an increment that results in one or more of the unmasked bits of the counter being ?0? will de-assert the counter interrupt flag. the example in figure 2 shows the counter mask register loaded with a mask value of 0003fh unmasking the first 6 bits with bit ?0? as the lsb and bit ?16? as the msb. the maximum value the mask register can be loaded with is 3ffffh. setting the mask register to this value allows the counter to access the entire memory space. the address counter is then loaded with an initial value of 8h. the base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. the counter address will start at address 8h. the counter will increment its internal address value till it reaches the mask register val ue of 3fh. the counter wraps around the memory block to location 8h at the next count. cntint is issued when the counter reaches its maximum value. counter hold operation the value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. such operation is useful in applic ations where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface. counter interrupt the counter interrupt (cntint ) is asserted low when an increment operation results in the unmasked portion of the counter register being all ?1s.? it is deasserted high when an increment operation results in any other value. it is also de-asserted by counter reset, counter load, mask reset and mask load operations, and by mrst . counter readback operation the internal value of the counte r register can be read out on the address lines. readback is pipelined; the address will be valid t ca2 after the next rising edge of the port?s clock. if address readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. retransmit retransmit is a feature that allows the read of a block of memory more than once without the need to reload the initial address. this eliminates the need for external logic to store and route data. it also reduces the complexity of the system design and saves board space. an internal ?mirror register? is used to store the initially loaded address counter value. when the counter unmasked portion reaches its maximum value set by the mask register, it wraps ba ck to the initial value stored in this ?mirror register.? if the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the ?mirror register.? thus, the repeated access of the same data is allowed without the need for any external logic. mask reset operation the mask register is reset to all ?1s,? which unmasks every bit of the counter. master reset (mrst ) also resets the mask register to all ?1s.? mask load operation the mask register is loaded with the address value presented at the address lines. not all values permit correct increment operations. permitted values are of the form 2 n ? 1 or 2 n ? 2. from the most significant bit to the least significant bit, permitted values have zero or more ?0s,? one or more ?1s,? or one ?0.? thus 7ffff, 003fe, and 00001 are permitted values, but 7f0ff, 003fc, and 00000 are not. mask readback operation the internal value of the mask register can be read out on the address lines. readback is pipelined; the address will be valid t cm2 after the next rising edge of the port?s clock. if mask readback occurs while the port is enabled (ce0 low and ce1 high), the data lines (dqs) will be three-stated. figure 1 shows a block diagram of the operation. counting by two when the least significant bit of the mask register is ?0,? the counter increments by two. this may be used to connect the x36 devices as a 72-bit single port sram in which the counter of one port counts even addresse s and the counter of the other port counts odd addresses. this even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations. note: 20. cntint and cntrst specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 8 of 28 from mask register mirror counter address decode ram array wrap 1 0 increment logic 1 0 +1 +2 1 0 wrap detect from mask from counter to counter bit 0 wrap figure 1. counter, mask, an d mirror logic block diagram [1] 17 17 17 17 17 1 0 load/increment cnt/msk cnten ads cntrst clk decode logic bidirectional address lines mask register counter/ address register from address lines to readback and address decode 17 17 mrst
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 9 of 28 ieee 1149.1 serial boundary scan (jtag) [22] the flex36 family devices in corporate an ieee 1149.1 serial boundary scan test access port (tap). the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant taps. the tap operates using jedec-standard 3.3v i/o logic levels. it is composed of three input connections and one output connection required by the test logic defined by the standard. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the devices, and may be performed while the device is operating. an mrst must be performed on the devices after power-up. performing a pause/restart when a shift-dr pause-dr shift-dr is performed the scan chain will output the next bit in the chain twice. for example, if the value expected from the chain is 1010101, the device will output a 11010101. this extra bit will cause some testers to report an erroneous failure for the devices in a scan test. therefore the tester should be configured to never enter the pause-dr state. boundary scan hierarchy for 9-mbit and 18-mbit devices internally, the devices have mu ltiple dies. each die contains all the circuitry required to support boundary scan testing. the circuitry includes the tap, tap controller, instruction register, and data registers. the circui ty and operation of the die boundary scan are described in detail below. the scan chain for 9-mbit and 18-mbit devices uses a hierar- chical approach as shown in figure 3 and figure 4 . tms and tck are connected in parallel to each die to drive all 2- or 4-tap controllers in unison. in many cases, each die will be supplied with the same instruction. in other cases, it might be useful to supply different in structions to each die. one example would be testing the device id of one die while bypassing the rest. each pin of the devices is typically connected to multiple dies. for connectivity testing with the extest instruction, it is desirable to check the internal connections between dies as well as the external connections to the package. this can be accomplished by merging the netli st of the devices with the netlist of the user?s circuit board. to facilitate boundary scan testing of the devices, cypress provides the bsdl file for each die, the internal netlist of the device, and a description of the device scan chain. the user can use these materials to easily integrate the devices into the board?s boundary scan environment. further information can be found in the cypress application note using jtag boundary scan for system in a package (sip) dual-port srams . notes: 21. the ?x? in this diagram represents the counter upper bits. 22. boundary scan is ieee 1149.1-compatible. see ?performing a pause/restart? for deviation from strict 1149.1 compliance. 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 2 16 2 15 2 6 2 1 2 5 2 2 2 4 2 3 2 0 h h l h 11 0s 1 0 1 0 1 01 00 xs 1 x 0 x 0 x0 11 xs 1 x 1 x 1 x1 00 xs 1 x 0 x 0 x0 masked address unmasked address mask register bit-0 address counter bit-0 cntint example: load counter-mask register = 3f load address counter = 8 max address register max + 1 address register figure 2. programmable counter-mask register operation [1, 21]
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 10 of 28 d2 tdi tdo tdo tdi d1 tdo tdi d4 tdo tdi d3 tdo tdi figure 3. scan chain for 18-mbit device d2 tdo tdi d1 tdo tdi tdi tdo figure 4. scan chain for 9-mbit device table 4. identification register definitions instruction field value description revision number (31:28) 0h reserved for version number. cypress device id (27:12) c002h defines cypress part number for cyd04s36v, cyd09s36v and cyd18s36v c001h defines cypress part number for CYD02S36V c092h defines cypress part number for cyd01s36v cypress jedec id (11:1) 034h allows unique ident ification of the dp family device vendor. id register presence (0) 1 indicates the presence of an id register. table 5. scan register sizes register name bit size instruction 4 bypass 1 identification 32 boundary scan n [23] note: 23. see details in the device bsdl files.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 11 of 28 table 6. instruction identification codes instruction code description extest 0000 captures the input/output ring cont ents. places the bsr between the tdi and tdo. bypass 1111 places the byr between tdi and tdo. idcode 1011 loads the idr with the vendor id code and places the register between tdi and tdo. highz 0111 places byr between tdi and tdo. forces all device output drivers to a high-z state. clamp 0100 controls boundary to 1/0. places byr between tdi and tdo. sample/preload 1000 captures the input/output ring contents. places bsr between tdi and tdo. nbsrst 1100 resets the non-boundary scan logic. places byr between tdi and tdo. reserved all other codes other co mbinations are reserved. do not use other than the above.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 12 of 28 maximum ratings [24] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................. .............. .. ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential ............... ?0.5v to +4.6v dc voltage applied to outputs in high-z state...........................?0.5v to v dd +0.5v dc input voltage ............ .................. ?0.5v to v dd + 0.5v [25] output current into outputs (low)............................. 20 ma static discharge voltage......... .............. .............. ...... > 2000v (jedec jesd22-a114-2000b) latch-up current..................................................... > 200 ma operating range range ambient temperature v ddio/vttl v core commercial 0c to +70c 3.3v165 mv 1.8v100 mv industrial ?40c to +85c 3.3v165 mv 1.8v100 mv electrical characteristics over the operating range pa- rame- ter description -167 -133 -100 unit min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v dd = min., i oh = ?4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v dd = min., i ol = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ?10 10 ?10 10 ?10 10 ua i ix1 input leakage current except tdi, tms, mrst ?10 10 ?10 10 ?10 10 ua i ix2 input leakage current tdi, tms, mrst ?1.0 0.1 ?1.0 0.1 ?1.0 0.1 ma i cc operating current for (v dd = max.,i out = 0 ma), outputs disabled cyd01s36v CYD02S36V/ cyd04s36v 225 300 225 300 ma cyd09s36v 450 600 370 540 cyd18s36v 410 580 315 450 i sb1 [26] standby current (both ports ttl level) ce l and ce r ? v ih , f = f max 90 115 90 115 ma i sb2 [26] standby current (one port ttl level) ce l | ce r ? v ih , f = f max 160 210 160 210 ma i sb3 [26] standby current (both ports cmos level) ce l and ce r ? v dd ? 0.2v, f = 0 55 75 55 75 ma i sb4 [26] standby current (one port cmos level) ce l | ce r ? v ih , f = f max 160 210 160 210 ma i sb5 operating current (vddio =max,iout=0ma,f=0) outputs disabled cyd18s36v 75 75 ma i core core operating current for (v dd = max.,i out = 0 ma), outputs disabled 00 0 0 0 0ma capacitance [27] part number parameter description test conditions max. unit cyd01s36/ CYD02S36V/ cyd04s36v c in input capacitance t a = 25c, f = 1 mhz, v dd = 3.3v 13 pf c out output capacitance 10 pf cyd09s36v c in input capacitance 22 pf c out output capacitance 10 [28] pf note: 24. the voltage on any input or i/o pin can not exceed the power pin during power-up. 25. pulse width < 20 ns. 26. i sb1 , i sb2 , i sb3 and i sb4 are not applicable for cyd18s36v because it cann ot be powered down by using chip enable pins. 27. c out also references c i/o . 28. except int and cntint which are 20 pf.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 13 of 28 ac test load and waveforms cyd18s36v c in input capacitance 40 pf c out output capacitance 20 pf capacitance [27] part number parameter description test conditions max. unit switching characteristics over the operating range parameter description -167 -133 -100 unit cyd01s36v CYD02S36V cyd04s36v cyd09s36v cyd01s36v CYD02S36V cyd04s36v cyd09s36v cyd18s36v cyd18s36v min. max. min. max. min. max. min. max. f max2 maximum operating frequency 167 133 133 100 mhz t cyc2 clock cycle time 6.0 7.5 7.5 10.0 ns t ch2 clock high time 2.7 3.0 3.4 4.5 ns t cl2 clock low time 2.7 3.0 3.4 4.5 ns t r [29] clock rise time 2.0 2.0 2.0 3.0 ns t f [29] clock fall time 2.0 2.0 2.0 3.0 ns t sa address set-up time 2.3 2.5 2.2 2.7 ns t ha address hold time 0.6 0.6 1.0 1.0 ns t sb byte select set-up time 2.3 2.5 2.2 2.7 ns t hb byte select hold time 0.6 0.6 1.0 1.0 ns t sc chip enable set-up time 2.3 2.5 na na ns t hc chip enable hold time 0.6 0.6 na na ns t sw r/w set-up time 2.3 2.5 2.2 2.7 ns t hw r/w hold time 0.6 0.6 1.0 1.0 ns t sd input data set-up time 2.3 2.5 2.2 2.7 ns t hd input data hold time 0.6 0.6 1.0 1.0 ns t sad ads set-up time 2.3 2.5 na na ns t had ads hold time 0.6 0.6 na na ns t scn cnten set-up time 2.3 2.5 na na ns t hcn cnten hold time 0.6 0.6 na na ns t srst cntrst set-up time 2.3 2.5 na na ns t hrst cntrst hold time 0.6 0.6 na na ns r1 = 590 ? r2 = 435 ? c = 5 pf (b) three-state delay (load 2) 90% 10% 3.0v vss 90% 10% <2ns <2ns all input pulses 3.3v v th = 1.5v r = 50 ? z 0 = 50 ? (a) normal load (load 1) c = 10 pf output output
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 14 of 28 t scm cnt/msk set-up time 2.3 2.5 na na ns t hcm cnt/msk hold time 0.6 0.6 na na ns t oe output enable to data valid 4.0 4.4 5.5 5.5 ns note: 29. except jtag signals (t r and t f < 10 ns [max.]). t olz [30, 31] oe to low z 0 0 0 0 ns t ohz [30, 31] oe to high z 0 4.0 0 4.4 0 5.5 0 5.5 ns t cd2 clock to data valid 4.0 4.4 5.0 5.2 ns t ca2 clock to counter address valid 4.0 4.4 na na ns t cm2 clock to mask register readback valid 4.0 4.4 na na ns t dc data output hold after clock high 1.0 1.0 1.0 1.0 ns t ckhz [30, 31] clock high to output high z 0 4.0 0 4.4 0 4.7 0 5.0 ns t cklz [30, 31] clock high to output low z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns t sint clock to int set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10.0 ns t rint clock to int reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10.0 ns t scint clock to cntint set time 0.5 5.0 0.5 5.7 na na na na ns t rcint clock to cntint reset time 0.5 5.0 0.5 5.7 na na na na ns port to port delays t ccs clock to clock skew 5.2 6.0 5.7 8.0 ns master reset timing t rs master reset pulse width 5.0 5.0 5.0 5.0 cycles t rs master reset set-up time 6.0 6.0 6.0 8.5 ns t rsr master reset recovery time 5.0 5.0 5.0 5.0 cycles t rsf master reset to outputs inactive 10.0 10.0 10.0 10.0 ns t rsint master reset to counter and mailbox interrupt flag reset time 10.0 10.0 na na ns jtag timing parameter description 167/133/100 unit min. max. f jtag maximum jtag tap controller frequency 10 mhz t tcyc tck clock cycle time 100 ns t th tck clock high time 40 ns t tl tck clock low time 40 ns t tmss tms set-up to tck clock rise 10 ns t tmsh tms hold after tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t tdih tdi hold after tck clock rise 10 ns t tdov tck clock low to tdo valid 30 ns t tdox tck clock low to tdo invalid 0 ns switching characteristics over the operatin g range (continued) parameter description -167 -133 -100 unit cyd01s36v CYD02S36V cyd04s36v cyd09s36v cyd01s36v CYD02S36V cyd04s36v cyd09s36v cyd18s36v cyd18s36v min. max. min. max. min. max. min. max.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 15 of 28 jtag switching waveform notes: 30. this parameter is guaranteed by design, but it is not production tested. 31. test conditions used are load 2. jtag timing test clock test mode select tck tms test data-in tdi te s t d a ta - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdox t tdov switching waveforms master reset mrst t rsr t rs inactive active tms tdo int cntint t rsf t rss all address/ data lines all other inputs t rsint
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 16 of 28 read cycle [13, 32, 33, 34, 35] notes: 32. oe is asynchronously controlled; all other inputs (excluding mrst and jtag) are synchronous to the rising clock edge. 33. ads = cnten = low, and mrst = cntrst = cnt/msk = high. 34. the output is disabled (high-impedance state) by ce = v ih following the next rising edge of the clock. 35. addresses do not have to be accessed sequentially since ads = cnten = v il with cnt/msk = v ih constantly loads the address on the rising edge of the clk. numbers are for reference only. switching waveforms (continued) t ch2 t cl2 t cyc2 t sc t hc t sw t hw t sa t ha a n a n+1 clk ce r/w address data out oe a n+2 a n+3 t sc t hc t ohz t oe t olz t dc t cd2 t cklz q n q n+1 q n+2 1 latency be0 ?be3 t sb t hb
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 17 of 28 bank select read [36, 37] read-to-write -to-read (oe = low) [35, 38, 39, 40, 41] notes: 36. in this depth-expansion example, b1 represents bank #1 and b2 is bank #2; each bank consists of one cypress flex36 device fr om this data sheet. address (b1) = address (b2) . 37. ads = cnten = be0 ? be3 = oe = low; mrst = cntrst = cnt/msk = high. 38. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 39. during ?no operation,? data in memory at the selected address may be corrupted and should be rewritten to ensure data integr ity. 40. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 41. ce 0 = be0 ? be3 = r/w = low; ce 1 = cntrst = mrst = cnt/msk = high. when r/w first switches low, since oe = low, the write operation cannot be completed (labelled as no operation). one clock cycle is required to three-state the i/o for the write operation on the next ri sing edge of clk. switching waveforms (continued) q 3 q 1 q 0 q 2 a 0 a 1 a 2 a 3 a 4 a 5 q 4 a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha t sc t hc t sa t ha t sc t hc t sc t hc t sc t hc t ckhz t dc t dc t cd2 t cklz t cd2 t cd2 t ckhz t cklz t cd2 t ckhz t cklz t cd2 t ch2 t cl2 t cyc2 clk address (b1) ce (b1) data out(b2) data out(b1) address (b2) ce (b2) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa t hw t sw t cd2 t dc t sd t hd write clk ce r/w address data in data out a n a n+1 a n+2 a n+2 d n+2 a n+2 a n+3 q n t ckhz no operation read
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 18 of 28 read-to-write -to-read (oe controlled) [35, 38, 40, 41] read with address counter advance [40] switching waveforms (continued) t cyc2 t cl2 t ch2 t hc t sc t hw t sw t ha t sa a n a n+1 a n+2 a n+3 a n+4 a n+5 t hw t sw t sd t hd d n+2 t cd2 t ohz read read write d n+3 q n clk ce r/w address data in data out oe q n+4 t cd2 t sa t ha t ch2 t cl2 t cyc2 clk address a n counter hold read with counter t sad t had t scn t hcn t sad t had t scn t hcn q x?1 q x q n q n+1 q n+2 q n+3 t dc t cd2 read with counter read external address ads cnten data out
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 19 of 28 write with address counter advance [41] switching waveforms (continued) t ch2 t cl2 t cyc2 a n a n+1 a n+2 a n+3 a n+4 d n+1 d n+1 d n+2 d n+3 d n+4 a n d n t sad t had t scn t hcn t sd t hd write external write with counter address write with counter write counter hold clk address internal data in address t sa t ha cnten ads
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 20 of 28 counter reset [42, 43] notes: 42. ce 0 = be0 ? be3 = low; ce 1 = mrst = cnt/msk = high. 43. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset. switching waveforms (continued) clk address internal cnten ads data in address cntrst r/w data out a n a m a p a x 0 1 a n a m a p q 1 q n q 0 d 0 t ch2 t cl2 t cyc2 t sa t ha t sw t hw t srst t hrst t sd t hd t cd2 t cd2 t cklz [55] reset address 0 counter write read address 0 address 1 read read address a n address a m read
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 21 of 28 readback state of address counter or mask register [44, 45, 46, 47] notes: 44. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 45. address in output mode. host must not be driving address bus after t cklz in next clock cycle. 46. address in input mode. host can drive address bus after t ckhz . 47. an * is the internal value of the address counter (or the mask register depending on the cnt/msk level) being read out on the address lines. switching waveforms (continued) cnten clk t ch2 t cl2 t cyc2 address ads a n q x-2 q x-1 q n t sa t ha t sad t had t scn t hcn load address external t cd2 internal address a n+1 a n+2 a n t ckhz data out a n* q n+3 q n+1 q n+2 a n+3 a n+4 t cklz t ca2 or t cm2 readback internal counter address increment external a 0 ?a 16
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 22 of 28 left_port (l_port) write to right_port (r_port) read [48, 49, 50] notes: 48. ce 0 = oe = ads = cnten = be0 ? be3 = low; ce 1 = cntrst = mrst = cnt/msk = high. 49. this timing is valid when one port is writing, and other port is reading the same location at the same time. if t ccs is violated, indeterminate data will be read out. 50. if t ccs < minimum specified value, then r_port will read t he most recent data (written by l_port) only (2 * t cyc2 + t cd2 ) after the rising edge of r_port's clock. if t ccs > minimum specified value, then r_port will read the most recent data (written by l_port) (t cyc2 + t cd2 ) after the rising edge of r_port's clock. switching waveforms (continued) t sa t ha t sw t hw t ch2 t cl2 t cyc2 clk l r/w l a n d n t ckhz t hd t sa a n t ha q n t dc t ccs t sd t cklz t ch2 t cl2 t cyc2 t cd2 l_port address l_port data in clk r r/w r r_port address r_port data out
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 23 of 28 counter interrup t and retransmit [16, 51, 52, 53, 54, 55] notes: 51. ce 0 = oe = be0 ? be3 = low; ce 1 = r/w = cntrst = mrst = high. 52. cntint is always driven. 53. cntint goes low when the unmasked portion of the addres s counter is incremented to the maximum value. 54. the mask register assumed to have the value of 3ffffh. 55. retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. switching waveforms (continued) t ch2 t cl2 t cyc2 clk 3fffd 3ffff internal address last_loaded last_loaded +1 t hcm counter 3fffe cntint t scint t rcint 3fffc cnten ads cnt/msk t scm
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 24 of 28 mailbox interrupt timing [56, 57, 58, 59, 60] switching waveforms (continued) t ch2 t cl2 t cyc2 clk l t ch2 t cl2 t cyc2 clk r 7ffff t sa t ha a n+3 a n a n+1 a n+2 l_port address a m a m+4 a m+1 7ffff a m+3 r_port address int r t sa t ha t sint t rint table 7. read/write and enable operation (any port) [1, 17, 61, 62, 63] inputs outputs operation oe clk ce 0 ce 1 r/w dq 0 ? dq 35 x h x x high-z deselected x x l x high-z deselected xlhld in write llhhd out read h x l h x high-z outputs disabled notes: 56. ce 0 = oe = ads = cnten = low; ce 1 = cntrst = mrst = cnt/msk = high. 57. address ?7ffff? is the mailbox location for r_port of the 9-mbit device. 58. l_port is configured for write operation, and r_port is configured for read operation. 59. at least one byte enable (be0 ? be3 ) is required to be active during interrupt operations. 60. interrupt flag is set with respect to the rising edge of the wr ite clock, and is reset with respect to the rising edge of th e read clock. 61. oe is an asynchronous input signal. 62. when ce changes state, deselection and read happen after one cycle of latency. 63. ce 0 = oe = low; ce 1 = r/w = high.
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 25 of 28 ordering information 512k 36 (18-mbit) 3.3v synchronous cyd18s36v dual-port sram speed( mhz) ordering code package name package type operating range 133 cyd18s36v-133bbc bb256 256-ball grid array 23 mm 23 mm with 1.0-mm pitch (bga) commercial 100 cyd18s36v-100bbc bb256 256-ball grid array 23 mm 23 mm with 1.0-mm pitch (bga) commercial cyd18s36v-100bbi bb256 256-ball grid array 23 mm 23 mm with 1.0-mm pitch (bga) industrial 256k 36 (9-mbit) 3.3v synchronous cyd09s36v dual-port sram speed( mhz) ordering code package name package type operating range 167 cyd09s36v-167bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial 133 cyd09s36v-133bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial cyd09s36v-133bbi bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) industrial 128k 36 (4-mbit) 3.3v synchronous cyd04s36v dual-port sram speed( mhz) ordering code package name package type operating range 167 cyd04s36v-167bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial 133 cyd04s36v-133bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial cyd04s36v-133bbi bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) industrial 64k 36 (2-mbit) 3.3v synchronous CYD02S36V dual-port sram speed( mhz) ordering code package name package type operating range 167 CYD02S36V-167bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial 133 CYD02S36V-133bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial CYD02S36V-133bbi bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) industrial 32k 36 (1-mbit) 3.3v synchronous cyd01s36v dual-port sram speed( mhz) ordering code package name package type operating range 167 cyd01s36v-167bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial 133 cyd01s36v-133bbc bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) commercial cyd01s36v-133bbi bb256 256-ball grid array 17 mm 17 mm with 1.0-mm pitch (bga) industrial
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 26 of 28 package diagrams bottom view top view 10987654321 a b c d e f g h j k pin 1 corner pin 1 corner 0.20(4x) ?0.25mcab ?0.05 m c ?0.450.05(256x)-cpld devices (37k & 39k) 0.25 c 0.700.05 c seating plane 0.15 c 16 15 14 13 12 11 t r p m n l n t r p m l k j f g h e d a c b 16 15 13 14 12 10 11 9 28 7 6 5 4 3 1 a b ?0.50 (256x)-all other devices +0.10 -0.05 a1 0.36 0.56 a 1.40 max. 1.70 max. reference jedec mo-192 15.00 1.00 0.35 a 17.000.10 7.50 7.50 15.00 17.000.10 1.00 a1 -0.05 +0.10 256-ball fbga (17 x 17 mm) bb256 51-85108-*f
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 27 of 28 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. flex36 is a trademark of cypress semiconductor corporation. a ll product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 256-ball fbga (23 mm x 23 mm x 1.7 mm) bb256b 51-85201-**
preliminary cyd01s36v CYD02S36V/cyd04s36v cyd09s36v/cyd18s36v document #: 38-06076 rev. *b page 28 of 28 document history page document title: flex36 ? 3.3v 32k/64k/128k/256k/512 x 36 synchronous dual-port ram document number: 38-06076 rev. ecn no. issue date orig. of change description of change ** 232012 see ecn wwz new data sheet *a 244232 see ecn wwz changed pinout changed ftsel# to ftsel in the block diagram *b 313156 see ecn ydt changed pinout d10 from nc to vss to refl ect test mode pin swap, c10 from rev[2,4] to vss to reflect sc removal. changed trscntint to trsint added trsint to the master reset timing diagram added cyd01s36v to datasheet added i sb5 and changed i ix2

▲Up To Search▲

Price & Availability of CYD02S36V

	To Download CYD02S36V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .